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EL1881C
EL1881C
Sync Separator, Low Power
Features
* NTSC, PAL, SECAM, nonstandard video sync separation * Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P * Low supply current - 1.5mA typ. * Single +5V supply * Composite, vertical sync output * Odd/even field output * Burst/back porch output * Available in 8-pin PDIP and SO packages
General Description
The EL1881C video sync separator is manufactured using Elantec's high performance analog CMOS process. This device extracts sync timing information from both standard and non-standard video input. It provides composite sync, vertical sync, burst/back porch timing, and odd/even field detection. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and 2VP-P (sync tip amplitude 143mV to 572mV). A single external resistor sets all internal timing to adjust for various video standards. The composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The odd/even output indicates field polarity detected during the vertical blanking interval. The EL1881C is plug-in compatible with the industry-standard LM1881 and can be substituted for that part in 5V applications with lower required supply current. The EL1881C is available in the 8-pin PDIP and SO packages and is specified for operation over the full -40C to +85C temperature range.
Applications
* * * * * * * * * Video amplifiers PCMCIA applications A/D drivers Line drivers Portable computers High-speed communications RGB applications Broadcast equipment Active filtering
Connection Diagram
Ordering Information
Part No. EL1881CN EL1881CS EL1881CS-T7 EL1881CS-T13 Package 8-Pin PDIP 8-Pin SO 8-Pin SO 8-Pin SO Tape & Reel 7" 13" Outline # MDP0031 MDP0027 MDP0027 MDP0027
Composite Sync Out 1 Composite Video In 2 Vertical Sync Out 3 GND 4
8 VDD 5V 7 Odd/Even Output 6 RSET 5 Burst/Back Porch Output
Demo Board
A dedicated demo board is available.
September 18, 2001
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
(c) 2001 Elantec Semiconductor, Inc.
EL1881C
EL1881C
Sync Separator, Low Power
Absolute Maximum Ratings (T
VCC Supply Storage Temperature Pin Voltages
A
= 25C)
7V -65C to +150C -0.5V to VCC +0.5V
Operating Ambient Temperature Range Operating Junction Temperature Power Dissipation
-40C to +85C 150C 400mW
Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA.
DC Characteristics
VDD = 5V, TA = 25C, RSET = 681k, unless otherwise specified. Parameter IDD, Quiescent Clamp Voltage Clamp Discharge Current Clamp Charge Current RSET Pin Reference Voltage VOL Output Low Voltage VOH Output High Voltage VDD = 5V Pin 2, ILOAD = -100A Pin 2 = 2V Pin 2 = 1V Pin 6 IOL = 1.6mA IOH = -40A IOH = -1.6mA 4 3 Description Min 0.75 1.35 6 -1.3 1.1 Typ 1.5 1.5 12 -1 1.22 0.24 4.8 4.6 Max 3 1.65 16 0.7 1.35 0.5 Unit mA V A mA V V V
Dynamic Characteristics
Parameter Comp Sync Prop Delay, tCS Vertical Sync Width, tVS Vertical Sync Default Delay, tVSD Burst/Back Porch Delay, tBD Burst/Back Porch Width, tB Input Dynamic Range Slice Level See Figure 2 Normal or Default Trigger, 50%-50% See Figure 3 See Figure 2 See Figure 2 Video Input Amplitude to Maintain 50% Slice Spec VSLICE/VCLAMP Description Min 20 190 35 120 2.5 0.5 55 70 Typ 35 230 62 200 3.5 Max 75 300 85 300 4.5 2 85 Unit ns s s ns s VP-P mV
2
EL1881C
EL1881C
Sync Separator, Low Power
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 Pin Name Composite Sync Out Composite Video In Vertical Sync Out GND Burst/Back Porch Output RSET [1] Odd/Even Output VDD 5V Pin Function Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase) Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period Supply ground Burst/back porch output; low during burst portion of composite video An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for NTSC signals Odd/even field output; high during odd fields, low during even fields; transitions occur at start of vert sync pulse Positive supply (5V)
1. RSET must be a 1% resistor
3
EL1881C
EL1881C
Sync Separator, Low Power
Typical Performance Curves
Supply Current vs Temperature RSET=681k 5.5V 5V Supply Current (mA) 1.55 1.5 1.45 1.4 1.35 -50 1.495 1.485 -50 4.5V VCLAMP (V) 1.515 1.505 VCLAMP Voltage vs Temperature RSET=681k 5.5V 1.525 4.5V 5V
1.65 1.6
1.535
-25
0
25 Temperature (C)
50
75
100
-25
0
25 Temperature (C)
50
75
100
11.4 11.3 Clamp Discharge Current (A) 11.2 11.1 11 10.9 10.8
Clamp Discharge Current vs Temperature RSET=681k
1.24 1.235
VRSET vs Temperature RSET=681k 5.5V 5V 4.5V
5.5V 5V 4.5V
1.23 VRSET (V) 50 75 100 1.225 1.22 1.215 1.21 1.205
10.7 -50
-25
0
25 Temperature (C)
1.2 -50
-25
0
25 Temperature (C)
50
75
100
1.1 1.05 1
Clamp Charge Current vs Temperature RSET=681k
RSET vs Horizontal Frequency 1000 800 600 400 200 0 10
Clamp Charge Current (mA)
5.5V
5V 0.95 0.9 0.85 -50
4.5V
-25
0
25 Temperature (C)
50
75
100
RSET (k)
15
20
25
30
35
40
45
Frequency (kHz)
4
EL1881C
EL1881C
Sync Separator, Low Power
Typical Performance Curves
Burst/Back Porch Width vs RSET VDD=5V, TA=25C Burst/Back Porch Delay vs RSET VDD=5V, TA=25C
6 5 Burst Width (S) 4 3 2
350 300 Burst/Back Porch Delay (ns) 250 200 150 100 50
1 200
400
600 RSET (k)
800
1000
0 200
400
600 RSET (k)
800
1000
350 300 250 200 150 100 50
Vertical Sync Width vs RSET VDD=5V, TA=25C
120 100 80 60 40 20
Vertical Default Delay vs RSET VDD=5V, TA=25C
Vertical Sync Default Delay (S)
Vertical Sync Width (S)
0 200
400
600 RSET (k)
800
1000
0 200
400
600 RSET (k)
800
1000
Composite Sync Prop Delay vs Temperature 41 39 37 35 33 31 -50 3.9 3.8 Composite Sync Prop Delay (ns) Burst/Back Porch Width (S) 3.7 3.6 3.5 3.4 3.3 3.2 -25 0 25 Temperature (C) 50 75 100
Burst/Back Porch Width vs Temperature
5.5V 5V 4.5V
3.1 -50
-25
0
25 Temperature (C)
50
75
100
5
EL1881C
EL1881C
Sync Separator, Low Power
Typical Performance Curves
Burst/Back Porch Delay vs Temperature RSET=681k 5.5V Vertical Sync Pulse Width (s) Burst/Back Porch Delay (ns) 200 150 100 50 0 -50 5V 237 5V 235 233 231 229 -50 Vertical Sync Pulse Width vs Temperature RSET=681k 5.5V
250
239
4.5V
4.5V
-25
0
25 Temperature (C)
50
75
100
-25
0
25 Temperature (C)
50
75
100
64.5 Vertical Sync Default Delay Time (S) 63.5 62.5 61.5 60.5
Vertical Sync Default Delay Time vs Temperature RSET=681k
20 18 16 14 12
Composite Sync to Vertical Sync Delay Time RSET=681k
5.5V
4.5V
tCS-VS (ns)
5V
5V 5.5V
4.5V
59.5 -50
-25
0
25 Temperature (C)
50
75
100
10 -50
-25
0
25 Temperature (C)
50
75
100
27 25 23 tCS-OE (ns) 21 19 17
Composite Sync to Odd/Even Delay Time RSET=681k
1.4 1.2
Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
4.5V Power Dissipation (W) 5V
1.25W
JA =
1 0.8 781mW 0.6 0.4 0.2 0
10
PD IP 8 0 C/ W
SO 8 60 C/W
J
A=1
5.5V
15 -50
-25
0
25 Temperature (C)
50
75
100
0
25
50
75 85
100
125
150
Ambient Temperature (C)
6
EL1881C
EL1881C
Sync Separator, Low Power
Timing Diagrams
Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). * Signal 1a drawing reproduced with permission from EIA.
Figure 1. Standard (NTSC Input) Timing
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EL1881C
EL1881C
Sync Separator, Low Power
Expanded Timing Diagrams
Figure 2. Standard Vertical Timing
Figure 3. Non-Standard Vertical Timing
8
EL1881C
EL1881C
Sync Separator, Low Power
Figure 4. Standard (NTSC Input) H. Sync Detail
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EL1881C
EL1881C
Sync Separator, Low Power
Applications Information
Video In
A simplified block diagram is shown following page. An AC coupled video signal is input to Video In pin 2 via C1, nominally 0.1F. Clamp charge current will prevent the signal on pin 2 from going any more negative than Sync Tip Ref, about 1.5V. This charge current is nominally about 1mA. A clamp discharge current of about 10A is always attempting to discharge C1 to Sync Tip Ref, thus charge is lost between sync pulses that must be replaced during sync pulses. The droop voltage that will occur can be calculated from IT = CV, where V is the droop voltage, I is the discharge current, T is the time between sync pulses (sync period - sync tip width), and C is C1. An NTSC video signal has a horizontal frequency of 15.73kHz, and a sync tip width of 4.7s. This gives a period of 63.6s and a time T = 58.9s. The droop voltage will then be V = 5.9mV. This is less than 2% of a nominal sync tip amplitude of 286mV. The charge represented by this droop is replaced in a time given by T = CV/I, where I = clamp charge current = 1mA. Here T = 590ns, about 12% of the sync pulse width of 4.7s. It is important to choose C1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. Vertical Sync is clocked out of the EL1881C on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60S after the last falling edge of the vertical equalizing phase for RSET = 681k.
Odd/Even
Because a typical television picture is composed of two interlaced fields, there is an odd field that includes all the odd lines, and an even field that consists of the even lines. This odd/even field information is decoded by the EL1881C during the end of picture information and the beginning of vertical information. The odd/even circuit includes a T-flip-flop that is reset during full horizontal lines, but not during half lines or vertical equalization pulses. The T-flip-flop is clocked during each falling edge of these half hperiod pulses. Even fields will toggle until a low state is clocked to the odd/even pin 7 at the beginning of vertical sync, and odd fields will cause a high state to be clocked to the odd/even pin at the start of the next vertical sync pulse. Odd/even can be ignored if using non-interlaced video, as there is no change in timing from one field to the next.
Fixed Gain Buffer
The clamped video signal then passes to the fixed gain buffer which places the sync slice level at the equivalent level of 70mV above sync tip. The output of this buffer is presented to the comparator, along with the slice reference. The comparator output is level shifted and buffered to TTL levels, and sent out as Composite Sync to pin 1.
RSET
An external RSET resistor, connected from RSET pin 6 to ground, produces a reference current that is used internally as the timing reference for vertical sync width, vertical sync default delay, burst gate delay and burst width. Decreasing the value of RSET increases the reference current, which in turn decreases reference times and pulse widths. A higher frequency video input necessitates a lower RSET value.
Burst
A low-going Burst pulse follows each rising edge of sync, and lasts approximately 3.5s for an RSET of 681k.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the incoming video signal. Use of the optional chroma filter is shown in Figure 5. It can be implemented very simply and inexpensively with a series resistor of 620 and a parallel capacitor of 500pF, which gives a single
10
Vertical Sync
A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal.
EL1881C
EL1881C
Sync Separator, Low Power
pole roll-off frequency of about 500kHz. This sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes the approximately 15kHz sync signals without appreciable attenuation. A chroma filter will increase the propagation delay from the composite input to the outputs.
Figure 5.
Simplified Block Diagram
* Note: RSET must be a 1% resistor.
Figure 6.
11
EL1881C
EL1881C
Sync Separator, Low Power
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
September 18, 2001
Elantec Semiconductor, Inc.
675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323 (888) ELANTEC Fax: (408) 945-9305 European Office: 44-118-977-6020 Japan Technical Center: 81-45-682-5820
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Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.'s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Printed in U.S.A.

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